A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

Description This work introduces the design and simulation of a low standby power and enhanced static noise margin (SNM) optimized 10-transistor (10T) SRAM cell. Since standard 6T and 8T SRAM cells are challenged by considerable limitations in read stability and leakage power with state-of-the-art nanometer-scale technology, the new 10T cell overcomes these challenges via architectural improvements. The architecture involves decoupled read and write paths and adds power-gating transistors to minimize leakage current while in standby mode, drastically reducing power consumption without sacrificing access speed. In order to measure the performance of the cell, the whole design is synthesized and simulated by means of the HSPICE tool, which enables exact transistor-level analysis. Important performance parameters like average power, delay, SNM, and power-delay product (PDP) are obtained with different supply voltages and process corners. The outputs are compared with conventional SRAM structures, showing significant increases in robustness and energy efficiency. The project is well-suited to VLSI students and researchers seeking knowledge in the area of memory circuit design and supplies the full package from schematic to waveform analysis based on industry-standard simulation tools.